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| 1 TC820 3-3/4 DIGIT A/D CONVERTER WITH FREQUENCY COUNTER AND LOGIC PROBE FEATURES s Multiple Analog Measurement System -- Digit A/D Converter -- Frequency Counter -- Logic Probe s Low Noise A/D Converter: -- Differential Inputs, (1pA Bias Current) -- On-Chip 50PPM/C Voltage Reference s Frequency Counter: -- 4Mhz Maximum Input Frequency -- Auto-ranging Over Four Decade Range s Logic Probe: -- Two LCD Annunciators -- Buzzer Driver s 3-3/4 Digit Display with Overrange Indicator s LCD Display Driver with Built-in Contrast Control s Data Hold Input for Comparison Measurements s Low Battery Detect with LCD Annunciator s Underrange and Overrange Outputs s On-Chip Buzzer Driver with Control Input s 44-Pin Plastic Flat Pack or PLCC or 40-Pin Plastic DIP Packages 2 3 4 Temperature Range GENERAL DESCRIPTION The TC820 is a 3-3/4 digit, multi-measurement system especially suited for use in portable instruments. It integrates a dual slope A/D converter, auto-ranging frequency counter and logic probe into a single 44-pin surface mount or 40-pin through hole package. The TC820 operates from a single 9V input voltage (battery) and features a built-in battery low flag. Function and decimal point selection are accomplished with simple logic inputs designed for direct connection to an external microcontroller or rotary switch. Ease of use, low power operation and high functional integration make the TC820 desirable in a variety of analog measurement applications. ORDERING INFORMATION Part No. TC820CKW TC820CLW Resolution 3-3/4 Digits 3-3/4 Digits Package TC820CPL 3-3/4 Digits 44-Pin Plastic 0C to +70C Quad Flat Package 44-Pin Plastic 0C to +70C Leadless Chip Carrier 40-Pin Plastic DIP 0C to +70C 5 6 FUNCTIONAL BLOCK DIAGRAM TRIPLEX LCD LOGIC HIGH LOGIC LOW OVERRANGE PKHOLD LOW BATT ANNUNCIATOR DRIVE LOW DRIFT VOLTAGE DIFFERENTIAL REFERENCE CLOCK OSCILLATOR TRIPLE LCD DRIVERS EOC UNDERRANGE OVERRANGE ANALOG INPUT FULL-SCALE SELECT FREQUENCY INPUT 3-3/4 DIGIT A/D CONVERTER ANALOG GND PEAK HOLD COMPARATOR DECIMAL POINT DRIVERS DECIMAL POINT SELECT AUTORANGING FREQUENCY COUNTER LOGIC PROBE DIGITAL GROUND LOW BATTERY DETECT BUZZER DRIVER BUZZER CONTROL FUNCTION SELECT VOLTS FREQUENCY LOGIC FUNCTION SELECT 7 TC820 TO LCD AND BUZZER LOGIC PROBE INPUT + PEAK HOLD 9V 8 TC820-10 10/17/96 TELCOM SEMICONDUCTOR, INC. 3-149 3-3/4 DIGIT A/D CONVERTER WITH FREQUENCY AND LOGIC PROBE TC820 GENERAL DESCRIPTION The TC820 is a 3-3/4 digit measurement system combining an integrating analog-to-digital converter, frequency counter, and logic level tester in a single package. The TC820 supersedes the TC7106 in new designs by improving performance and reducing system cost. The TC820 adds features that are difficult, expensive, or impossible to provide with older A/D converters (see the competitive evaluation). The high level of integration permits TC820based instruments to deliver higher performance and more features, while actually reducing parts count. Fabricated in low-power CMOS, the TC820 directly drives a 3-3/4 digit (3999 maximum) LCD. With a maximum range of 3999 counts, the TC820 provides 10 times greater resolution in the 200mV to 400mV range than traditional 3-1/2 digit meters. An auto-zero cycle guarantees a zero reading with a 0V input. CMOS processing reduces analog input bias current to only 1pA. Rollover error (the difference in readings for equal magnitude but opposite polarity input signals) is less than 1 count. Differential reference inputs permit ratiometric measurements for ohms or bridge transducer applications. The TC820's frequency counter option simplifies design of an instrument well-suited to both analog and digital troubleshooting: voltage, current, and resistance measurements, plus precise frequency measurements to 4MHz (higher frequencies can be measured with an external prescaler), and a simple logic probe. The frequency counter will automatically adjust its range to match the input frequency, over a four-decade range. Two logic level measurement inputs permit a TC820based meter to function as a logic probe. When combined with external level shifters, the TC820 will display logic levels on the LCD and also turn on a piezoelectric buzzer when the measured logic level is low. Other TC820 features simplify instrument design and reduce parts count. On-chip decimal point drivers are included, as is a low battery detection annunciator. A piezoelectric buzzer can be controlled with an external switch or by the logic probe inputs. Two oscillator options are provided: A crystal can be used if high accuracy frequency measurements are desired, or a simple RC option can be used for low-end instruments. A "peak reading hold" input allows the TC820 to retain the highest A/D or frequency reading. This feature is useful in measuring motor starting current, maximum temperature, and similar applications. A family of instruments can be created with the TC820. No additional design effort is required to create instruments with 3-3/4 digit resolution. The TC820 operates from a single 9V battery, with typical power of 10 mW. Packages include a 40-pin plastic DIP, 44-pin plastic flat package, and 44-pin PLCC. COMPETITIVE EVALUATION Features Comparison 3-3/4 Digit Resolution Auto-Ranging Frequency Counter Logic Probe Decimal Point Drive Peak Reading Hold (Frequency or Voltage) Display Hold Simple 10:1 Range Change Buzzer Drive Low Battery Detection With Annunciator Overrange Detection With Annunciator Low Drift Reference Underrange/Overrange Logic Output Input Overload Display LCD Annunciator Driver LCD Drive Type LCD Pin Connections LCD Elements TC820 Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes "OL" Yes Triplexed 15 36 7106 No No No No No No No No No No No No "1" No Direct 24 23 3-150 TELCOM SEMICONDUCTOR, INC. 3-3/4 DIGIT A/D CONVERTER WITH FREQUENCY AND LOGIC PROBE TC820 ABSOLUTE MAXIMUM RATINGS* Supply Voltage (VDD to GND) .....................................15V Analog Input Voltage (Either Input) (Note 1) .... VDD to VSS Reference Input Voltage (Either Input) ............. VDD to VSS Digital Inputs ............................................... VDD to DGND VDISP ............................................. VDD to (DGND - 0.3V) Package Power Dissipation (TA 70C) (Note 2) 40-Pin Plastic DIP ............................................. 1.23W 44-Pin PLCC .....................................................1.23W 44-Pin Plastic Flat Package .............................. 1.00W Operating Temperature Range "C" Devices ............................................ 0C to +70C "E" Devices ....................................... - 40C to +85C Storage Temperature Range ................ - 65C to +150C Lead Temperature (Soldering, 10 sec) ................... 300C *Static-sensitive devices. Unused devices should be stored in conductive material to protect against static discharge and static fields. Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions above those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. NOTES: 1. Input voltages may exceed the supply voltages provided that input current is limited to 100A. Current above this value may result in invalid display readings but will not destroy the device if limited to 1mA. 2. Dissipation ratings assume device is mounted with all leads soldered to printed circuit board. 1 2 3 4 5 6 7 ELECTRICAL CHARACTERISTICS: VS = 9V, TA = 25C, unless otherwise specified. Symbol Parameter Zero Input Reading RE NL Roll-Over Error Nonlinearity (Maximum Deviation From Best Straight Line Fit) Ratiometric Reading Common-Mode Rejection Ratio Common-Mode Voltage Range Noise (P-P Value Not Exceeded 95% of Time) Input Leakage Current Test Conditions VIN = 0V Full Scale = 400 mV VIN = 390mV Full-Scale = 400mV Full-Scale = 400mV Min - 000 -1 -1 Typ 000 0.2 0.2 Max +000 +1 +1 Units Digital Reading Counts Count CMRR VCMR eN IIN VIN = VREF, TC820 VCM = 1V, VIN = 0V Full-Scale = 400mV (VFS = 200 mV) Input High, Input Low VIN = 0V Full-Scale = 400mV VIN = 0V TA = 25C 0C TA +70C - 40C TA +85C 25 k Between Common and VDD (VSS - VCOM) 25 k Between Common and VDD 0C TA +70C - 40C TA +85C VIN = 0V 0C TA +70C - 40C TA +85C VIN = 399mV 0C TA +70C - 40C TA +85C Ext Ref = 0 ppm/C VIN = 0V VS = 9V VDISP = DGND 1999 -- 1999/2000 50 2000 -- Digital V/V VSS + 1.5 -- -- 15 VDD- 1 -- V V -- -- -- 3.15 -- -- -- 1 20 100 3.3 35 50 0.2 1 1 5 1 4.7 10 -- -- 3.45 50 -- -- pA VCOM VCTC Analog Common Voltage Common Voltage Temperature Coefficient Zero Reading Drift V ppm/C V/C TCZS TCFS Scale Factor Temperature Coefficient -- -- -- 4.25 5 -- 1.5 5.3 ppm/C IS Supply Current Peak-to-Peak Backplane Drive Voltage mA V 8 TELCOM SEMICONDUCTOR, INC. 3-151 3-3/4 A/D CONVERTER WITH FREQUENCY COUNTER AND LOGIC PROBE TC820 ELECTRICAL CHARACTERISTICS (Cont.) Symbol Parameter Buzzer Frequency Counter Timebase Period Low Battery Flag Voltage Input Low Voltage Input High Voltage Output Low Voltage, UR, OR Outputs Output High Voltage, UR, OR Outputs Control Pin Pull-Down Current Test Conditions fOSC = 40kHz fOSC = 40kHz VDD to VSS Min -- -- 6.7 -- VDD - 1.5 -- VDD - 1.5 -- Typ 5 1 7 -- -- -- -- 5 Max -- -- 7.3 DGND + 1.5 -- DGND + 0.4 -- -- Units kHz Second V V V V V A VIL VIH VOL VOL IL = 50A IL = 50A VIN = VDD PIN DESCRIPTION Pin No. (40-Pin Package) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 -- 16 17 Pin No. (44-Pin Flat Package) 40 41 42 43 44 1 2 3 4 5 6 7 8 9 10 11 12 13 Symbol L-E4 AGD4 BC4P3 HFE3 AGD3 BC3P2 OFE2 AGD2 BC2P1 PKFE1 AGD1 BC1BT BP3 BP2 BP1 VDISP DGND ANNUNC Description LCD segment driver for L ("logic LOW"), polarity, and "e" segment of most significant digit (MSD). LCD segment drive for "a," "g," and "d" segments of MSD. LCD segment drive for "b" and "c" segments of MSD and decimal point 3. LCD segment drive for H ("logic HIGH"), and "f" and "e" segments of third LSD. LCD segment drive for "a," "g," and "d" segments of third LSD. LCD segment drive for "b" and "c" segments of third LSD and decimal point 2. LCD segment drive for "overrange," and "f" and "e" segments of second LSD. LCD segment drive for "a," "g," and "d" segments of second LSD. LCD segment drive for "b " and "c" segments of second LSD and decimal point 1. LCD segment drive for "hold peak reading," and "f" and "e" segments of LSD. LCD segment drive for "a," "g," and "d" segments of LSD. LCD segment drive for "b" and "c" segments of LSD and "low battery." LCD backplane #3. LCD backplane #2. LCD backplane #1. Sets peak LCD drive signal: VPEAK = (VDD ) -VDISP. VDISP may also be used to compensate for temperature variation of LCD crystal threshold voltage. Internal logic digital ground, the logic "0" level. Nominally 4.7V below VDD. Square-wave output at the backplane frequency, synchronized to BP1. ANNUNC can be used to control display annunciators. Connecting an LCD segment to ANNUNC turns it on; connecting it to its backplane turns it off. Logic mode control input. When connected to VDD, the converter is in logic mode. The LCD displays "OL" and the decimal point inputs control the HIGH and LOW annunciators. When the "low" annunciator is on, the buzzer will also be on. When unconnected or connected to DGND, the TC820 is in the voltage/frequency measurement mode. This pin has a 5A internal pull-down to DGND. Dual-purpose input. In range mode, when connected to VDD, the integration time will be 200 counts instead of 2000 counts and the LCD will display the analog input divided by 10. (See text for limitation with TC820.) In frequency mode, this pin is the frequency input. A digital signal applied to this pin will be measured with a 1-second time base. There is an internal 5A pull-down to DGND. 18 14 LOGIC 19 15 RANGE/ FREQ 3-152 TELCOM SEMICONDUCTOR, INC. 3-3/4 A/D CONVERTER WITH FREQUENCY COUNTER AND LOGIC PROBE TC820 PIN DESCRIPTION Pin No. (40-Pin Package) 20 1 Pin No. (44-Pin Flat Package) 16 2 Symbol DP0/LO Description Dual-purpose input. Decimal point select input for voltage measurements. In logic mode, connecting this pin to VDD will turn on the "low" LCD segment. There is an internal 5A pull-down to DGND in volts mode only. Decimal point logic: DP1 DP0 Decimal Point Selected 0 0 None 0 1 DP1 1 0 DP2 1 1 DP3 Dual-purpose input. Decimal point select input for voltage measurements. In logic mode, connecting this pin to VDD will turn on the "high" LCD segment. There is an internal 5A pull-down to DGND in volts mode only. Buzzer output. Audio frequency, 5kHz, output which drives a piezoelectric buzzer. Buzzer control input. Connecting BUZIN to VDD turns the buzzer on. BUZIN is logically ORed (internally) with the "logic level low" input. There is an internal 5A pull-down to DGND. Voltage or frequency measurement select input. When unconnected, or connected to DGND, the A/D converter function is active. When connected to VDD, the frequency counter function is active. This pin has an internal 5A pull-down to DGND. Peak hold input. When connected to VDD, the converter will only update the display if a new conversion value is greater than the preceding value. Thus, the peak reading will be stored and held indefinitely. When unconnected, or connected to DGND, the converter will operate normally. This pin has an internal 5A pull-down to DGND. Underrange output. This output will be HIGH when the digital reading is 380 counts or less. Overrange output. This output will be HIGH when the analog signal input is greater than full scale. The LCD will display "OL" when the input is overranged. Negative supply connection. Connect to negative terminal of 9V battery. Analog circuit ground reference point. Nominally 3.3V below VDD. Positive connection for reference capacitor. Negative connection for reference capacitor. High differential reference input connection. Low differential reference input connection. Low analog input signal connection. High analog input signal connection. Buffer output. Connect to integration resistor. Auto-zero capacitor connection. Integrator output. Connect to integration capacitor. Bidirectional pin. Pulses low (i.e., from VDD to DGND) at the end of each conversion. If connected to VDD, conversions will continue, but the display is not updated. Crystal oscillator (input) connection. Crystal oscillator (output) connection. RC oscillator connection. Positive power supply connection, typically 9V. 3 4 5 6 7 21 17 DP1/HI 22 23 18 19 BUZOUT BUZIN 24 20 FREQ/ VOLTS 25 21 PKHOLD 22 23 26 27 28 29 30 31 32 33 34 35 36 24 25 26 27 28 29 30 31 32 33 34 35 UR OR VSS COM + CREF - CREF + VREF - VREF - VIN + VIN VBUFF CAZ VINT EOC/ HOLD OSC1 OSC2 OSC3 VDD 37 38 39 40 36 37 38 39 8 TELCOM SEMICONDUCTOR, INC. 3-153 3-3/4 A/D CONVERTER WITH FREQUENCY COUNTER AND LOGIC PROBE TC820 PIN CONFIGURATIONS EOC/HOLD 41 BC4P3 AGD3 OSC3 OSC2 AGD4 OSC1 HFE3 L-E4 6 5 4 3 2 VDD 1 44 43 42 40 BC3P2 OFE2 AGD2 VINT 39 C AZ 38 VBUFF 37 VIN 36 V IN 35 VREF 7 8 9 + - - BC2P1 10 PKFE1 11 AGD1 12 TC820CLW 34 V+ - REF BP1BT 13 33 CREF 32 CREF 31 COM 30 VSS 29 OR 18 19 20 21 22 23 24 25 SEGMENTS L-E4 SEGMENTS AGD4 SEGMENTS BC4P3 SEGMENTS HFE3 SEGMENTS AGD3 SEGMENTS BC3P2 SEGMENTS OFE2 SEGMENTS AGD2 SEGMENTS BCP1 1 2 3 4 5 6 7 8 9 40 VDD 39 OSC3 BP3 14 + BP2 15 BP1 16 38 OSC2 37 OSC1 36 V INT 35 CAZ 34 V BUFF + 33 V IN - 32 V IN - 31 V REF + 30 V REF - 29 CREF + 28 CREF 27 COM 26 VSS 25 PK HOLD 24 FREQ/VOLTS 23 BUZ IN 22 BUZ OUT 21 DP1/HI V DISP 17 26 27 28 FREQ/VOLTS RANGE/FREQ PK HOLD EOC/HOLD 35 LOGIC DP0/LO DGND DP1/HI BUZ OUT ANNUNC BUZ IN SEGMENTS PKFE1 10 SEGMENTS AGD1 11 SEGMENTS BC1BT 12 BP3 13 BP2 14 BP1 15 DGND 16 ANNUNC 17 LOGIC 18 RANGE/FREQ 19 DP0/LO 20 TC820CPL BC4P3 AGD3 AGD4 OSC3 OSC2 OSC1 HFE3 L-E4 44 43 42 41 40 39 38 37 36 34 V INT 33 C AZ 32 VBUFF 31 VIN 30 VIN 29 VREF BC3P2 1 OFE2 2 AGD2 3 BCP2P1 4 PKFE1 5 AGD1 6 VDD UR + - - TC820CKW 28 VREF 27 CREF 26 CREF 25 COM 24 V SS 23 OR + - BP1BT 7 BP3 8 BP2 9 + BP1 10 V DISP 11 12 13 14 15 16 17 18 19 20 21 22 RANGE/FREQ FREQ/VOLTS LOGIC DP0/LO DP1/HI BUZ OUT BUZ IN PK HOLD ANNUNC DGND 3-154 TELCOM SEMICONDUCTOR, INC. UR 3-3/4 A/D CONVERTER WITH FREQUENCY COUNTER AND LOGIC PROBE TC820 FUNCTIONAL BLOCK DIAGRAM 1 2 + CREF - CREF VBUFF CAZ VINT OSC1 OSC2 OSC3 LOGIC LOW + VIN - VIN + VREF - VREF COMMON VDD /8 /2 FREQUENCY COUNTER INPUT A/D COUNTER SELECT RANGE SEL A/D COUNTER B (3999 COUNTS) A RANGE/ FREQ FREQ/ VOLTS BUZZER DRIVER BUZ IN 3 4 LOW TO LCD BATT DETECT A/D CONTROL DEINT UNDERRANGE OVERRANGE EOC RANGE RANGE/FREQ INPUT TC820 COMPARATOR A>B DISPLAY LATCH LOGIC LOW LOW BATT TRIPLEX DRIVERS 15 LOGIC DP0/LO DP1/HI VSS 5 6 7 DGND UR OR EOC/ HOLD PEAK HOLD ANNUNC VDISP SEG0 * * * BP3 8 TELCOM SEMICONDUCTOR, INC. 3-155 3-3/4 A/D CONVERTER WITH FREQUENCY COUNTER AND LOGIC PROBE TC820 LOGIC HIGH LOGIC LOW OVERRANGE PKHOLD LOW BATT VDD NC 22k 2k VREF = 200mV 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 L-E4 AGD4 BC4P3 HFE3 AGD3 BC3P2 OFE2 AGD2 BC2P1 PK FE1 AGD1 BC1BT BP3 BP2 BP1 S1a FREQ/ 24 VOLTS TO SWITCH S2 18 LOGIC 100k 33 + VIN 0.01F 32 V - IN 16 DGND CHANGE COM RANGE 17 ANNUNC + VREF 30 - VREF 31 COM 27 VDD 40 + 9V VSS 26 - DGND BUZ OUT 22 PIEZO BUZZER DGND VDD VDD + 1F VDD VDD VIN GND S1b TC820 FREQ S1c VDD S1d VDD 19 RANGE/FREQ 20 DP0/LO BUZ IN 23 LOGIC S1e 21 DP1/HI OSC1 37 DP3 TO SWITCH S1a S2 DP2 DP1 NO DP 22M 40kHz OSC2 OSC3 VBUFF CAZ 38 470 k NC 39 34 100 k 35 0.47 F DGND PK HOLD 25 + - VINT CREF CREF 36 0.2 F 28 0.1 F 29 NOTE: Pin numbers are for 40-pin package. Figure 1. Typical Operating Circuit GENERAL THEORY OF OPERATION Dual-Slope Conversion Principles The TC820 analog-to-digital converter operates on the principle of dual-slope integration. An understanding of the dual-slope conversion technique will aid the user in following the detailed TC820 theory of operation following this section. A conventional dual-slope converter measurement cycle has two distinct phases: (1) Input Signal Integration (2) Reference Voltage Integration (Deintegration) Referring to Figure 2, the unknown input signal to be converted is integrated from zero for a fixed time period (t INT), measured by counting clock pulses. A constant reference voltage of the opposite polarity is then integrated until the integrator output voltage returns to zero. The reference integration (deintegration) time (TDEINT) is then directly proportional to the unknown input voltage (VIN). In a simple dual-slope converter, a complete conversion requires the integrator output to "ramp-up" from zero and "ramp-down" back to zero. A simple mathematical equation relates the input signal, reference voltage, and integration time: 3-156 ANALOG INPUT SIGNAL C R INTEGRATOR COMPARATOR - VIN = VFULL SCALE VIN = 1.2 VFULL SCALE VARIABLE REFERENCE INTEGRATE TIME + CLOCK COUNTER - SWITCH DRIVER REF VOLTAGE PHASE CONTROL CONTROL LOGIC POLARITY CONTROL DISPLAY INTEGRATOR OUTPUT FIXED SIGNAL INTEGRATE TIME Figure 2. Basic Dual-Slope Converter TELCOM SEMICONDUCTOR, INC. + 3-3/4 A/D CONVERTER WITH FREQUENCY COUNTER AND LOGIC PROBE TC820 1 RINT CINT 1 comparator) are removed from the conversion. A true digital zero reading is assured without any external adjustments. A complete conversion consists of four distinct phases: (1) (2) (3) (4) Zero Integrator Output Auto-Zero Signal Integrate Reference Deintegrate tINT 0 VREF tDEINT VIN (t) dt = RINT CINT 2 3 4 5 6 7 where: VREF = Reference voltage t INT = Integration time t DEINT = Deintegration time For a constant t INT: VIN = VREF t DEINT t INT Accuracy in a dual-slope converter is unrelated to the integrating resistor and capacitor values as long as they are stable during a measurement cycle. An inherent benefit of the dual-slope technique is noise immunity. Noise spikes are integrated or averaged to zero during the integration periods, making integrating ADCs immune to the large conversion errors that plague successive approximation converters in high-noise environments. Interfering signals, with frequency components at multiples of the averaging (integrating) period, will be attenuated (Figure 3). Integrating ADCs commonly operate with the signal integration period set to a multiple of the 50/60Hz power line period. Zero Integrator Output Phase This phase guarantees that the integrator output is at 0V before the system zero phase is entered, ensuring that the true system offset voltages will be compensated for even after an overrange conversion. The duration of this phase is 500 counts plus the unused deintegrate counts. Auto-Zero Phase During the auto-zero phase, the differential input signal is disconnected from the measurement circuit by opening internal analog switches, and the internal nodes are shorted to Analog Common (0VREF) to establish a zero input condition. Additional analog switches close a feedback loop around the integrator and comparator to permit comparator offset voltage error compensation. A voltage established on CAZ then compensates for internal device offset voltages during the measurement cycle. The auto-zero phase residual is typically 10V to 15V. The auto-zero duration is 1500 counts. Signal Integration Phase Upon completion of the auto-zero phase, the auto-zero loop is opened and the internal differential inputs connect to VIN+ and VIN-. The differential input signal is then integrated for a fixed time period, which is 2000 counts (4000 clock periods). The externally-set clock frequency is divided by two before clocking the internal counters. The integration time period is: t INT = 4000 fOSC NORMAL MODE REJECTION (dB) 30 T = MEASUREMENT PERIOD 20 10 0 0.1/T 1/T INPUT FREQUENCY 10/T Figure 3. Normal-Mode Rejection of Dual-Slope Converter Analog Section In addition to the basic integrate and deintegrate dualslope phases discussed above, the TC820 design incorporates a "zero integrator output" phase and an "auto-zero" phase. These additional phases ensure that the integrator starts at 0V (even after a severe overrange conversion), and that all offset voltage errors (buffer amplifier, integrator and TELCOM SEMICONDUCTOR, INC. The differential input voltage must be within the device's common-mode range when the converter and measured system share the same power supply common (ground). If the converter and measured system do not share the same power supply common, as in battery-powered applications, VIN- should be tied to analog common. Polarity is determined at the end of signal integration phase. The sign bit is a "true polarity" indication in that signals less than 1 LSB are correctly determined. This allows precision null detection that is limited only by device noise and auto-zero residual offsets. 8 3-157 3-3/4 A/D CONVERTER WITH FREQUENCY COUNTER AND LOGIC PROBE TC820 Reference Integrate (Deintegrate) Phase The reference capacitor, which was charged during the auto-zero phase, is connected to the input of the integrating amplifier. The internal sign logic ensures the polarity of the reference voltage is always connected in the phase opposite to that of the input voltage. This causes the integrator to ramp back to zero at a constant rate determined by the reference potential. The amount of time required (TDEINT) for the integrating amplifier to reach zero is directly proportional to the amplitude of the voltage that was put on the integrating capacitor (VINT) during the integration phase: t DEINT = RINT CINT VINT VREF The digital reading displayed by the TC820 is: Digital Count = 2000 + - VIN - VIN VREF System Timing The oscillator frequency is divided by 2 prior to clocking the internal decade counters. The four-phase measurement cycle takes a total of 8000 (4000) counts or 16000 clock pulses. The 8000 count phase is independent of input signal magnitude or polarity. Each phase of the measurement cycle has the following length: Conversion Phase 1) Auto-Zero: 2) Signal Integrate:1,2 3) Reference Integrate: 4) Integrator Output Zero: Peak Reading Hold The TC820 provides the capability of holding the highest (or peak) reading. Connecting the PK HOLD input to VDD enables the peak hold feature. At the end of each conversion the contents of the TC820 counter is compared to the contents of the display register. If the new reading is higher than the reading being displayed, the higher reading is transferred to the display register. A "higher" reading is defined as the reading with the higher absolute value. The peak reading is held in the display register so the reading will not "droop" or slowly decay with time. The held reading will be retained until a higher reading occurs, the PK HOLD input is disconnected from VDD, or power is removed. The peak signal to be measured must be present during the TC820 signal integrate period. The TC820 does not perform transient peak detection of the analog input signal. However, in many cases, such as measuring temperature or electric motor starting current, the TC820 "acquisition time" will not be a limitation. If true peak detection is required, a simple circuit will suffice. See the applications section for details. The peak reading function is also available when the TC820 is in the frequency counter mode. The counter autoranging feature is disabled when peak reading hold is selected. 10:1 Range Change The analog input full-scale range can be changed with the RANGE/FREQ input. Normally, RANGE/FREQ is held low by an internal pulldown. Connecting this pin to VS+ will increase the full-scale voltage by a factor of 10. No external component changes are required. The RANGE/FREQ input operates by changing the integrate period. When RANGE/FREQ is connected to VDD, the signal integration phase of the conversion is reduced by a factor of 10 (i.e., from 2000 counts to 200 counts). For the TC820, the 10:1 range change will result in 4V full scale. This full-scale range will exceed the commonmode range of the input buffer when operating from a 9V battery. If range changing is required for the TC820, a higher supply voltage can be provided or the input voltage can be divided by 2 externally. Counts 1500 2000 1 to 4001 499 to 4499 NOTES: 1. This time period is fixed. The integration period for the TC820 is: t INT (TC820) = 4000 fOSC = 2000 counts where fOSC is the clock oscillator frequency. 2. Times shown are the RANGE/FREQ at logic low (normal operation). When RANGE/FREQ is logic high, signal integrate times are 200 counts. See "10:1 Range Change" section. Frequency Counter In addition to serving as an analog-to-digital converter, the TC820 internal counter can also function as a frequency counter (Figure 4). In the counter mode, pulses at the RANGE/FREQ input will be counted and displayed. The frequency counter derives its time base from the clock oscillator. The counter time base is: tCOUNT = fOSC 40,000 TELCOM SEMICONDUCTOR, INC. Input Overrange When the analog input is greater than full scale, the LCD will display "OL" and the "OVERRANGE" LCD annunciator will be on. 3-158 3-3/4 A/D CONVERTER WITH FREQUENCY COUNTER AND LOGIC PROBE TC820 Thus, the counter will operate with a 1-second time base when a 40 kHz oscillator is used. The frequency counter accuracy is determined by the oscillator accuracy. For accurate frequency measurements, a crystal oscillator is recommended. The frequency counter will automatically select the proper range. Auto-range operation extends over four decades, from 3.999 kHz to 3.999 MHz. Decimal points are set automatically in the frequency mode (Figure 5). The logic switching levels of the RANGE/FREQ input are CMOS levels. For best counter operation, an external buffer is recommended. See the applications section for details. If the logic probe is active while FREQ/VOLTS is high (counter mode), the frequency counter will continue to operate. The display will read "OL" but the decimal points will be visible. If the logic probe input is also connected to the RANGE/FREQ input, bringing the LOGIC input low will immediately display the frequency at the logic probe input. 1 2 3 4 5 Analog Pin Functional Description + - Differential Signal Inputs (VIN), (VIN) The TC820 is designed with true differential inputs, and accepts input signals within the input stage common-mode voltage (VCM) range. The typical range is VDD -1V to VSS +1.5V. Common-mode voltages are removed from the system when the TC820 operates from a battery or floating power source (isolated from measured system) and VSS is connected to analog common. (See Figure 8.) Logic Probe The TC820 can also function as a simple logic probe (Figure 6). This mode is selected when the LOGIC input is high. Two dual-purpose pins, which normally control the decimal points, are used as logic inputs. Connecting either input to a logic high level will turn on the corresponding LCD annunciator. When the "low" annunciator is on the buzzer will be on. As with the frequency counter input, external level shifters/buffers are recommended for the logic probe inputs. When the logic probe function is selected while FREQ/ VOLTS is low (A/D mode), the ADC will remain in the autozero mode. The LCD will read "OL" and all decimal points will be off (Figure 7). LCD COMPARATOR FROM INTEGRATOR OF A/D CONVERTER CLOCK OSCILLATOR /2 DATA LATCH, PEAK HOLD REGISTER, LCD DECODER/DRIVERS 6 OVERRANGE DETECT /20,000 A/D CONVERTER/FREQUENCY COUNTER SELECT A/D CONVERTER FREQUENCY COUNTER ENABLE 3-3/4 DIGIT COUNTER COUNT OVERFLOW FREQ/ VOLTS 7 TC820 TO DECIMAL POINT DRIVERS UNDERRANGE DETECT RANGE/ FREQ FREQUENCY INPUT PROGRAMMABLE DIVIDER ( /1, 10, 100, 1000) AUTO-RANGE CONTROL Figure 4. TC820 Counter Operation 8 3-159 TELCOM SEMICONDUCTOR, INC. 3-3/4 A/D CONVERTER WITH FREQUENCY COUNTER AND LOGIC PROBE TC820 In systems where common-mode voltages exist, the 86dB common-mode rejection ratio minimizes error. Common-mode voltages do, however, affect the integrator output level. A worst-case condition exists if a large, positive VCM exists in conjunction with a full-scale, negative differential signal. The negative signal drives the integrator output positive along with VCM (Figure 9). For such applications, the integrator output swing can be reduced below the recommended 2V full-scale swing. The integrator output will swing within 0.3V of VDD or VDD without increased linearity error. Reference (VDD, VSS) The TC820 reference, like the analog signal input, has true differential inputs. In addition, the reference voltage can be generated anywhere within the power supply voltage of the converter. The differential reference inputs permit ratiometric measurements and simplify interfacing with sensors, such as load cells and temperature sensors. DP3 f IN 0Hz - 3999Hz 4kHz - 39.99kHz 40kHz - 399.9kHz 400kHz DP2 DP1 DECIMAL POINT DP3 DP2 DP1 NONE Figure 5. TC820 Auto-Range Decimal Point Selection vs Frequency Counter Input LCD HIGH LOW LOGIC PROBE INPUT EXTERNAL LOGIC LEVEL DETECTION AND PULSE STRETCHING CMOS LOGIC LEVELS DP0/LO LCD DRIVERS DP1/HI TC820 VDD LOGIC DISABLE A/D CONVERTER TO BUZZER NC Figure 6. Logic Probe Simplified Schematic 3-160 TELCOM SEMICONDUCTOR, INC. 3-3/4 A/D CONVERTER WITH FREQUENCY COUNTER AND LOGIC PROBE TC820 Analog Common The analog common pin is set at a voltage potential approximately 3.3V below VDD. This potential is guaranteed to be between 3.15V and 3.45V below VDD. Analog common is tied internally to an N-channel FET capable of sinking 3mA. This FET will hold the common line at 3.3V below VDD should an external load attempt to pull the common line toward VDD. Analog common source current is limited to 12A, and is therefore easily pulled to a more negative voltage (i.e., below VDD - 3.3V). + - The TC820 connects the internal VIN and VIN inputs to analog common during the auto-zero cycle. During the - reference integrate phase, VIN is connected to analog - common. If VIN is not externally connected to analog common, a common-mode voltage exists. This is rejected by the converter's 86dB common-mode rejection ratio. In battery- powered applications, analog common and VIN are usually connected, removing common-mode voltage concerns. In - systems where VIN is connected to the power supply ground or to a given voltage, analog common should be connected - to VIN. The analog common pin serves to set the analog section reference or common point. The TC820 is specifically designed to operate from a battery or in any measurement 1 HIGH * LOW ** 2 3 4 5 6 7 * "HIGH" ANNUNCIATOR WILL BE ON WHEN DP1/HI = ** LOGIC HIGH "LOW" ANNUNCIATOR AND BUZZER WILL BE ON WHEN DP0/LO = LOGIC HIGH Figure 7. LCD During Logic Probe Operation To prevent roll-over-type errors from being induced by large common-mode voltages, CREF should be large compared to stray node capacitance. A 0.1F capacitor is typical. The TC820 offers a significantly improved analog common temperature coefficient, providing a very stable voltage suitable for use as a voltage reference. The temperature coefficient of analog common is typically 35ppm/C. SEGMENT DRIVE LCD BP1 MEASURED SYSTEM V + - BP3 BP2 OSC1 VIN VIN - + VBUF CAZ VINT TC820 OSC2 VSS OSC3 NC V + - GND ANALOG + - COMMON VREF VREF VDD + 9V VV POWER GND SOURCE - Figure 8. Common-Mode Voltage Removed in Battery Operation With VIN = Analog Common 8 TELCOM SEMICONDUCTOR, INC. 3-161 3-3/4 A/D CONVERTER WITH FREQUENCY COUNTER AND LOGIC PROBE TC820 INPUT BUFFER + - VIN - VI = VCM TI V CM - VIN RI CI + INTEGRATOR CI RI - VI + FREQ/VOLTS This input determines whether the TC820 is in the analog-to-digital conversion mode or in the frequency counter mode. When FREQ/VOLTS is connected to VDD, the TC820 will measure frequency at the RANGE/FREQ input. When unconnected, or connected to DGND, the TC820 will operate as an analog-to-digital converter. This input has an internal 5A pull-down to DGND. LOGIC The LOGIC input is used to activate the logic probe function. When connected to VDD, the TC820 will enter the logic probe mode. The LCD will show "OL" and all decimal points will be off. The decimal point inputs directly control "high" and "low" display annunciators. When LOGIC is unconnected, or connected to DGND, the TC820 will perform analog-to-digital or frequency measurements as selected by the FREQ/VOLTS input. The LOGIC input has an internal 5 A pull-down to DGND. RANGE/FREQ The function of this dual-purpose pin is determined by the FREQ/VOLTS input. When FREQ/VOLTS is connected to VDD, RANGE/FREQ is the input for the frequency counter function. Pulses at this input are counted with a time base equal to fOSC/40,000. Since this input has CMOS input levels (VDD - 1.5V and DGND +1.5V), an external buffer is recommended. When the TC820 analog-to-digital converter function is selected, connecting RANGE/FREQ to VDD will divide the integration time by 10. Therefore, the RANGE/FREQ input can be used to perform a 10:1 range change without changing external components. DP0/LO, DP1/HI The function of these dual-purpose pins is determined by the LOGIC input. When the TC820 is in the analog-todigital converter mode, these inputs control the LCD decimal points. The decimal point truth table is shown in Table II. These inputs have internal 5A pull-downs to DGND when the voltage/frequency measurement mode is active. Table II. TC820 Decimal Point Truth Table Decimal Point Inputs DP1 0 0 1 1 [ [ Where: TI= Integration Time = 4000 fOSC C I = Integration Capacitor R I = Integration Resistor Figure 9. Common-Mode Voltage Reduces Available Integrator Swing (VCOM VIN) system where input signals are not referenced (float) with respect to the TC820 power source. The analog common potential of VDD - 3.3V gives a 7V end-of-battery-life voltage. The analog common potential has a voltage coefficient of 0.001%/%. With a sufficiently high total supply voltage (VDD - VSS > 7V), analog common is a very stable potential with excellent temperature stability (typically 35ppm/C). This potential can be used to generate the TC820 reference voltage. An external voltage reference will be unnecessary in most cases, because of the 35ppm/C temperature coefficient. See the applications section for details. Function Control Input Pin Functional Description The TC820 operating modes are selected with the function control inputs. The control input truth table is shown in Table I. The high logic threshold is VDD - 1.5V and the low logic level is DGND +1.5V. Table I. TC820 Control Input Truth Table Logic Input FREQ/ VOLTS X 0 0 1 RANGE/ FREQ X 0 1 Frequency Counter Input LOGIC 1 0 0 0 TC820 Function Logic Probe A/D Converter, VFULL SCALE = 2 VREF A/D Converter, VFULL SCALE = 20 VREF Frequency Counter DP0 0 1 0 1 LCD 3999 399.9 39.99 3.999 NOTES: 1. Logic "0" = DGND 2. Logic "1" = VDD 3-162 TELCOM SEMICONDUCTOR, INC. 3-3/4 A/D CONVERTER WITH FREQUENCY COUNTER AND LOGIC PROBE TC820 Connecting the LOGIC input to VDD places the TC820 in the logic probe mode. In this mode, the DP0/LO and DP1/ HI inputs control the LCD "low" and "high" annunciators directly. When DP1/HI is connected to VDD, the "high" annunciator will turn on. When DP0/LO is connected to VDD, the "low" annunciator and the buzzer will turn on. The internal pull-downs on these pins are disabled when the logic probe function is selected. These inputs have CMOS logic switching thresholds. For optimum performance as a logic probe, external level shifters are recommended. See the applications section for details. BUZ IN This input controls the TC820 on-chip buzzer driver. Connecting BUZ IN to VDD will turn the buzzer on. There is an external pull-down to DGND. BUZ IN can be used with external circuitry to provide additional functions, such as a fast, audible continuity indication. 1 EOC/HOLD 4 DISPLAY UPDATE 2 3 4 5 500 k EOC TC820 Figure 10. EOC/HOLD Pin Schematic Additional Features The TC820 is available in 40-pin and 44-pin packages. Several additional features are available in the 44-pin package. EOC/HOLD EOC/HOLD is a dual-purpose, bidirectional pin. As an output, this pin goes low for 10 clock cycles at the end of each conversion. This pulse latches the conversion data into the display driver section of the TC820. EOC/HOLD can be used to hold (or "freeze") the display. Connecting this pin to VDD inhibits the display update process. Conversions will continue, but the display will not change. EOC/HOLD will hold the display reading for either analog-to-digital or frequency measurements. The input/output structure of the EOC/HOLD pin is shown in Figure 10. The output drive current is only a few microAmps, so EOC/HOLD can easily be overdriven by an open-collector logic gate, as well as a FET, bipolar transistor, or mechanical switch. When used as an output, EOC/ HOLD will have a slow rise and fall time due to the limited output current drive. A CMOS Schmitt trigger buffer is recommended. Overrange (OR), Underrange (UR) The OR output will be high when the analog input signal is greater than full scale (3999 counts). The UR output will be high when the display reading is 380 counts or less. The OR and UR outputs can be used to provide an autoranging meter function. By logically ANDing these outputs with the inverted EOC/HOLD output, a single pulse will be generated each time an underranged or overranged conversion occurs (Figure 11). EOC/HOLD * * * * 74HC132 TC820 UR OR 6 7 Figure 11. Generating Underrange and Overrange Pulses VDISP The VDISP input sets the peak-to-peak LCD drive voltage. In the 40-pin package, VDISP is connected internally to DGND, providing a typical LCD drive voltage of 5VP-P. The 44-pin package includes a separate VDISP input for applications requiring a variable or temperature-compensated LCD drive voltage. See the applications information for suggested circuits. 8 TELCOM SEMICONDUCTOR, INC. 3-163 3-3/4 A/D CONVERTER WITH FREQUENCY COUNTER AND LOGIC PROBE TC820 VDISP The VDISP input sets the peak-to-peak LCD drive voltage. In the 40-pin package, VDISP is connected internally to DGND, providing a typical LCD drive voltage of 5 VP-P. The 44-pin package includes a separate VDISP input for applications requiring a variable or temperature-compensated LCD drive voltage. See the applications information for suggested circuits. Digital Ground (DGND) Digital ground is generated from an internal zener diode (Figure 14). The voltage between VDD and DGND is the internal supply voltage for the digital section of the TC820. DGND will sink a minimum of 3mA. DGND establishes the low logic level reference for the TC820 mode select inputs, and for the frequency and logic probe inputs. The DGND pin can be used as the negative supply for external logic gates, such as the logic probe buffers. To ensure correct counter operation at high frequency, connect a 1F capacitor from DGND to VDD. DGND also provides the drive voltage for the LCD. The TC820 40-pin package internally connects the LCD VDISP pin to DGND, and provides an LCD drive voltage of about 5VP-P. In the 44-pin package, connecting the VDISP pin to DGND will provide a 5V LCD drive voltage. APPLICATIONS INFORMATION Power Supplies The TC820 is designed to operate from a single power supply such as a 9V battery (Figure 12). The converter will operate over a range of 7V to 15V. For battery operation, analog common (COM) provides a common-mode bias voltage (see analog common discussion in the theory of operation section). However, measurements cannot be referenced to battery ground. To do so will exceed the negative common-mode voltage limit. Digital Input Logic Levels Logic levels for the TC820 digital inputs are referenced to VDD and DGND. The high-level threshold is VDD - 1.5V and the low logic level is DGND +1.5V. In most cases, digital inputs will be connected directly to VDD with a mechanical switch. CMOS gates can also be used to control the logic inputs, as shown in the logic probe inputs section. VDD VREF + 9V - - VREF + TC820 COM + VIN + V IN + VDD 3.5V to 6V VREF VREF COM - + TC04 - VIN - VSS TC820 + VIN + VIN - VIN - 8 2 + 5 10F 4 VSS Figure 12. Powering the TC820 From a Single 9V Battery TC7660 3 10F + A battery with voltage between 3.5V and 7V can be used to power the TC820, when used with a voltage doubler, as shown in Figure 13. The voltage doubler uses the TC7660 and two external capacitors. With this configuration measurements can be referenced either to Analog Common or to battery ground. 3-164 Figure 13. Powering the TC820 From a Low-Voltage Battery TELCOM SEMICONDUCTOR, INC. 3-3/4 A/D CONVERTER WITH FREQUENCY COUNTER AND LOGIC PROBE TC820 VDD 12A 5V N + LOGIC SECTION 3.2V COM - 1 2 5pF 10pF TC820 37 P DGND 38 110k 75pF 39 TC820 N 3 4 5 6 7 VSS Figure 16. R-C Oscillator Circuit Figure 14. DGND and COM Outputs Clock Oscillator The TC820 oscillator can be controlled with either a crystal or with an inexpensive resistor-capacitor combination. The crystal circuit, shown in Figure 15, is recommended when high accuracy is required in the frequency counter mode. The 40kHz crystal is a standard frequency for ultrasonic alarms, and will provide a 1-second time base for the counter or 2.5 analog-to-digital conversions per second. Consult the crystal manufacturer for detailed applications information. Where low cost is important, the R-C circuit of Figure 16 can be used. The frequency of this circuit will be approximately: 0.3 fOSC = RC Typical values are R = 10k and C = 68pF. The resistor value should be 100k. For accurate frequency measurement, an R-C oscillator frequency of 40kHz is required. System Timing All system timing is derived from the clock oscillator. The clock oscillator is divided by 2 prior to clocking the A/D counters. The clock is also divided by 8 to drive the buzzer, by 240 to generate the LCD backplane frequency, and by 40,000 for the frequency counter time base. A simplified diagram of the system clock is shown in Figure 17. Component Value Selection Auto Zero Capacitor -- CAZ The value of the auto-zero capacitor (CAZ) has some influence on system noise. A 0.47F capacitor is recommended; a low dielectric absorption capacitor (Mylar) is required. Reference Voltage Capacitor -- CREF The reference voltage capacitor used to ramp the integrator output voltage back to zero during the reference integrate cycle is stored on CREF. A 0.1F capacitor is typical. A good quality, low leakage capacitor (such as Mylar) should be used. Integrating Capacitor -- CINT CINT should be selected to maximize integrator output voltage swing without causing output saturation. Analog common will normally supply the differential voltage reference. For this case, a 2V integrator output swing is optimum when the analog input is near full scale. For 2.5 readings/second (fOSC = 40kHz) and VFS = 400mV, a 0.22F value is suggested. If a different oscillator frequency is used, CINT must be changed in inverse proportion to maintain the 3-165 5 pF 10pF TC820 37 40kHz 38 470k 39 22 M Figure 15. Suggested Crystal Oscillator Circuit 8 TELCOM SEMICONDUCTOR, INC. 3-3/4 A/D CONVERTER WITH FREQUENCY COUNTER AND LOGIC PROBE TC820 R/C OSCILLATOR COMPONENTS Reference Voltage Selection A full-scale reading (4000 counts for TC820) requires the input signal be twice the reference voltage. Table III. Reference Voltage Selection XTAL OSCILLATOR COMPONENTS Full-Scale Input Voltage (VFS) (Note 1) OSC1 OSC2 OSC3 VREF Note 2 200mV 500mV 1V Resolution - 10 V 250V 500V 200mV 400mV 1V 2V (Notes 3, 4) TC820 A/D COUNTER /2 BUZZER /8 NOTES: 1. TC820 in A/D converter mode, RANGE/FREQ = logic low. 2. Not recommended. 3. VFS > 2V may exceed the input common mode range. See "10:1 Range Change" section. 4. Full-scale voltage values are not limited to the values shown. For example, TC820 VFS can be any value from 400mV to 2V. LCD BACKPLANE DRIVER /240 COUNTER TIME BASE /40,000 Figure 17. System Clock Generation nominal 2V integrator swing. An exact expression for CINT is: CINT = where: fOSC VFS RINT VINT 4000 VFS VINT RINT fOSC = Clock frequency = Full-scale input voltage = Integrating resistor = Desired full-scale integrator output swing In some applications, a scale factor other than unity may exist between a transducer output voltage and the required digital reading. Assume, for example, that a pressure transducer output is 800mV for 4000 lb/in2. Rather than dividing the input voltage by two, the reference voltage should be set to 400mV. This permits the transducer input to be used directly. The internal voltage reference potential available at analog common will normally be used to supply the converter's reference voltage. This potential is stable whenever the supply potential is greater than approximately 7V. The low-battery detection circuit and analog common operate from the same internal reference. This ensures that the low-battery annunciator will turn on at the time the internal reference begins to lose regulation. The TC820 can also operate with an external reference. Figure 18 shows internal and external reference applications. CINT must have low dielectric absorption to minimize roll-over error. A polypropylene capacitor is recommended. Integrating Resistor -- RINT The input buffer amplifier and integrator are designed with class A output stages. The integrator and buffer can supply 40A drive currents with negligible linearity errors. RINT is chosen to remain in the output stage linear drive region but not so large that printed circuit board leakage currents induce errors. For a 400mV full scale, RINT should be about 100k. 3-166 Ratiometric Resistance Measurements The TC820 true differential input and differential reference make ratiometric readings possible. In ratiometric operation, an unknown resistance is measured with respect to a known standard resistance. No accurately defined reference voltage is needed. The unknown resistance is put in series with a known standard and a current is passed through the pair (Figure 19). The voltage developed across the unknown is applied to the input and voltages across the known resistor TELCOM SEMICONDUCTOR, INC. 3-3/4 A/D CONVERTER WITH FREQUENCY COUNTER AND LOGIC PROBE TC820 9V 1 + V 22k 2k VDD 2k VREF + +9V + 1F VDD TC820 2 3 4 5 6 7 VSS VDD VREF + TC820 VREF ANALOG COMMON - TC820 VREF VREF - + TC04A 1.2V REF DGND FREQUENCY INPUT 74HC14 GND FREQ/VOLTS RANGE/FREQ COMMON SET VREF = 1/2 VFULL SCALE DGND (a) Internal Reference (b) External Reference Figure 20. Frequency Counter External Buffer Figure 18. Reference Voltage Connections Logic Probe Inputs VREF RSTANDARD VREF VIN RUNKNOWN - VIN + - + VDD LCD TC820 ANALOG COMMON Figure 19. Low Parts Count Ratiometric Resistance Measurement applied to the reference input. If the unknown equals the standard, the input voltage will equal the reference voltage and the display will read 2000. The displayed reading can be determined from the following expression: Displayed reading = RUNKNOWN RSTANDARD 2000 The DP0/LO and DP1/HI inputs provide the logic probe inputs when the LOGIC input is high. Driving either DP0/LO or DP1/HI to a logic high will turn on the appropriate LCD annunciator. When DP0/LO is high, the buzzer will be on. To provide a "single input" logic probe function, external buffers should be used. A simple circuit is shown in Figure 21. This circuit will turn the appropriate annunciator on for high and low level inputs. If carefully controlled logic thresholds are required, a window comparator can be used. Figure 22 shows a typical circuit. This circuit will turn on the high or low annunciators when the logic thresholds are exceeded, but the resistors connected from DP0/LO and DP1/HI to DGND will turn both annunciators off when the logic probe is unconnected. The TC820 logic inputs are not latched internally, so pulses of short duration will usually be difficult or impossible to see. To display short pulses properly, the input pulse should be "stretched." The circuit of Figure 22 shows cap- The display will overrange for values of RUNKNOWN 2 RSTANDARD. +9V VDD LOGIC LOGIC PROBE INPUT TC820 Buffering the FREQ Input When the FREQ/VOLTS input is high and the LOGIC input is low, the TC820 will count pulses at the RANGE/ FREQ input. The time base will be fOSC/40,000, or 1 second with a 40kHz clock. The signal to be measured should swing from VDD to DGND. The RANGE/FREQ input has CMOS input levels without hysteresis. For best results, especially with low-frequency sine-wave inputs, an external buffer with hysteresis should be added. A typical circuit is shown in Figure 20. TELCOM SEMICONDUCTOR, INC. * * DP1/HI DP0/LO DGND * 74HC14 Figure 21. Simple External Logic Probe Buffer 3-167 8 3-3/4 A/D CONVERTER WITH FREQUENCY COUNTER AND LOGIC PROBE TC820 +9V VDD R1 - VH 1M R2 - LOGIC PROBE INPUT 1M R3 + 1N4148 DP1/HI LOGIC +9V VDD PK HOLD 10k 1N4148 VIN 0.01F OFFSET NULL VSS + TC820 1N4148 DP0/LO + TL061 VIN + VL DGND NOTE: Select R1, R2, R3 for desired logic thresholds. Figure 22. Window Comparator Logic Probe acitors added across the input pull-down resistors to stretch the input pulse and permit viewing short-duration input pulses. depending on the displays values. Figure 25 shows a set of waveforms for the a, g, d outputs of one digit for several combinations of "on" segments. Table IV. LCD Backplane and Segment Assignments 44-Pin Flat Pkg Pin No. 40 41 42 43 44 1 2 3 4 5 6 7 8 9 10 External Peak Detection The TC820 will hold the highest A/D conversion or frequency reading indefinitely when the PK HOLD input is connected to VDD. However, the analog peak input must be present during the A/D converter's signal integrate period. For slowly changing signals, such as temperature, the peak reading will be properly converted and held. If rapidly changing analog signals must be held, an external peak detector should be added. An inexpensive circuit can be made from an op amp and a few discrete components, as shown in Figure 23. The droop rate of the external peak detector should be adjusted so that the held voltage will not decay below the desired accuracy level during the converter's 400msec conversion time. 40-Pin DIP Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Liquid Crystal Display (LCD) The TC820 drives a triplex (multiplexed 3:1) LCD with three backplanes. The LCD can include decimal points, polarity sign, and annunciators for overrange, peak hold, high and low logic levels, and low battery. Table IV shows the assignment of the display segments to the backplanes and segment drive lines. The backplane drive frequency is obtained by dividing the oscillator frequency by 240. Backplane waveforms are shown in Figure 24. These appear on outputs BP1, BP2, and BP3. They remain the same regardless of the segments being driven. Other display output lines have waveforms that vary 3-168 *Connect both pins 2 and 16 of LCD to TC820 BP3 output. - TC820 0V Figure 23. External Peak Detector LCD Display Pin No. 3 4 5 6 7 8 9 10 11 12 13 14 2,16* 1 15 BP1 LOW A4 B4 HIGH A3 B3 OVER A2 B2 PEAK A1 B1 -- -- BP1 BP2 "--" G4 C4 F3 G3 C3 F2 G2 C2 F1 G1 C1 -- BP2 -- BP3 E4 D4 DP3 E3 D3 DP2 E2 D2 DP1 E1 D1 BATT BP3 -- -- TELCOM SEMICONDUCTOR, INC. 3-3/4 A/D CONVERTER WITH FREQUENCY COUNTER AND LOGIC PROBE TC820 LCD Source BP1 1 BP2 Although most users will design their own custom LCD, a standard display for the TC820 (Figure 26), Part No. ST1355-M1, is available from: Crystaloid (USA) Crystaloid Electronics P.O. Box 628 5282 Hudson Dr. Hudson, OH 44238 Phone: (216) 655-2429 Fax: (216) 655-2176 VDD VH VL VDISP VDD VH VL VDISP VDD VH VL VDISP VDD VH 2 3 4 5 6 7 BP3 Figure 24. Backplane Waveforms Crystaloid (Europe) Rep France 102, rue des Nouvelles F92150 Suresnes France Phone: 33-1-42 04 29 25 Fax: 33-1-45 06 46 99 SEGMENT LINE ALL OFF Annunciator Output The annunciator output is a square wave running at the backplane frequency (for example, 167Hz when fOSC = 40kHz). The peak-to-peak amplitude is equal to (VDD - VDISP). Connecting an annunciator of the LCD to the annunciator output turns it on; connecting it to its backplane turns it off. a SEGMENT ON d, g OFF LCD Drive Voltage (VDISP) The peak-to-peak LCD drive voltage is equal to (VDD - VDISP). In the 40-pin dual-in-line package (DIP), VDISP is internally connected to DGND, providing a typical LCD drive voltage of 5VP-P. For applications with a wide temperature range, some LCDs require that the drive levels vary with temperature to maintain good viewing angle and display contrast. In this case, the TC820 44-pin package provides a pin connection for VDISP. Figure 27 shows TC820 circuits that can be adjusted to give a temperature compensation of about 10mV/C between VDD and VDISP. The diode between GND and VDISP should have a low turn-on voltage because VDISP cannot exceed 0.3V below GND. a, g ON d OFF ALL ON VL VDISP Figure 25. Typical Display Output Waveforms Crystal Source Two sources of the 40 kHz crystal are: Statek Corp. 512 N. Main St. Orange, CA 92668 Phone: (714) 639-7810 Fax: (714) 997-1256 Part #: CX-1V-40.0 SPK Electronics 2F-1, No. 312, Sec. 4, Jen Ai Rd Taipei, Taiwan R.O.C. Phone: (02) 754-2677 Fax: 886-2-708-4124 Part#: QRT-38-40.0kHz HIGH LOW OVER PEAK BATT PIN 1 Figure 26. Typical TC820 LCD 8 3-169 TELCOM SEMICONDUCTOR, INC. 3-3/4 A/D CONVERTER WITH FREQUENCY COUNTER AND LOGIC PROBE TC820 V + V + 1N4148 39k 200k 39 20k 39k 39 2N2222 TC820 11 VDISP DGND 18k 24 1N5817 11 12 TC820 VDISP DGND 24 TL071 1N5817 75k 3-170 + 12 5k - V - V - NOTE: Pin numbers shown are for 44-pin flat package. Figure 27. Temperature-Compensating Circuits TELCOM SEMICONDUCTOR, INC. |
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